The present invention relates to the technical field of semiconductor manufacture, and, particularly, to a method of fabricating a semiconductor device that must be operated at a high speed.
At the present time, in order to realize high speed operation of a MOS transistor constituting a MOS LSI, it has became important to decrease the sheet resistance of the source and drain electrodes, the contact resistance of an electrode and wiring, and the parasitic capacitance of the source and drain.
In order to cope with the requirement, a structure, in which the source and drain surface is subjected at once to silicidation in a self-aligning manner, is applied particularly to a semiconductor device that must be operated at a high speed. In this structure, the surface of the electrodes is covered with a silicide having a low resistance, such as titanium silicide (TiSi2), cobalt silicide (CoSi2) and the like, to decrease the sheet resistance, and the contact resistance with wiring can also be decreased to a large extent in comparison with the conventional metal-semiconductor contact. Since the area of the source and drain can be reduced, the parasitic capacitance can also be reduced. Furthermore, the so-called salicide (self-aligned silicide) technique, in which, upon subjecting the surface of the source and drain to silicidation, the upper part of a gate electrode is also simultaneously subjected to silicidation in a self-aligning manner, is also widely employed.
In the case where TiSi2 is used, it is constituted with a metastable phase (C45 structure) having a relatively high specific resistance and a stable phase (C54 structure) having a relatively low specific resistance. The conversion of the metastable phase (C45 structure) to the stable phase (C54 structure) can be conducted by a heat treatment at about 800xc2x0 C. However, the temperature must be increased with an increase in the fineness of the pattern. That is, it has been known that there is a thin line width effect, in which the phase transfer is difficult to achieve with a fine pattern (for example, 0.2 xcexckm or less). Therefore, in order to realize a fine pattern having a gate line width of 0.2 xcexckm or less, the heat treatment temperature for the phase transfer must be increased. Accordingly, the heat treatment temperature affects the fine source/drain diffusion layer.
A MOS LSI of recent years is constituted with a complementary MOS transistor for low electric power consumption. Therefore, it is necessary to form a silicide layer on silicon having various dopants, such as an N+-type single crystal silicon region (N-type source/drain), a P+-type single crystal silicon region (P-type source/drain), an N+-type polycrystalline silicon gate electrode and a P+-type polycrystalline silicon gate electrode. In the case of TiSi2 the formation temperature thereof is greatly influenced by the dopant. In general, the thickness on the N+-type silicon becomes from 60 to 70% of that on the P+-type silicon. This is because Ti attracts an N-type dopant, and, as a result, the silicidation reaction is inhibited.
On the other hand, instead of TiSi2 which has the above-mentioned problems, CoSi2 is being applied, since it has a small thin line effect and a small influence from the dopant.
A MOS type semiconductor device having a salicide structure, to which CoSi2 is applied, is disclosed, for example, in Japanese Patent Laid-Open No. 186085/1996 and Japanese Patent Laid-Open No. 274047/1996. According to these publications, the problems of increase in junction leakage electric current and deterioration in junction withstand voltage in applying CoSi2 and the solutions thereof are disclosed. The problems occur due to the following factors.
Before forming a cobalt film by sputtering, a spontaneous oxide film is formed on a surface of a diffusion layer, and when the formation of the cobalt layer and the first heat treatment are conducted under that condition, an interface between the diffusion layer and the CoSi film becomes non-uniform and uneven. An interface between the diffusion layer obtained by the second heat treatment and the CoSi2 film cannot escape from the influence of the form of the interface between the diffusion layer and the CoSi film. Furthermore, because an increase in volume is associated with the conversion from the CoSi film to the CoSi2 film, the distance between the PN junction interface of the diffusion layer and the uneven bottom surface of the CoSi2 film becomes small. Accordingly, an increase in junction leakage electric current and deterioration in junction withstand voltage in the diffusion layer are liable to occur.
According to the technique disclosed in the former publication, after removing the spontaneous oxide film on the surface of the diffusion layer by use of a hydrogen plasma in a vacuum apparatus, bis (methylcyclopentadienyl) cobalt is evaporated without breaking the vacuum, and a cobalt film is formed by a CVD method in which the gas is subjected to thermal decomposition.
According to the technique disclosed in the later publication, after removing the spontaneous oxide film on the surface of the diffusion layer by use of a hydrogen plasma in a vacuum apparatus, a cobalt film is formed by a CVD method in which an evaporated gas of bis (hexafluoroacetylacetonato) cobalt is reduced with a hydrogen gas without breaking the vacuum.
The present inventors have revealed that in the case of CoSi2, an increase in junction leakage electric current and deterioration in junction withstand voltage occurs due to the following problems that occur completely separately from the problem of increase in junction leakage electric current and deterioration in junction withstand voltage due to the spontaneous oxide film disclosed in the publications.
As one of the measures for preventing the junction leakage between the source/drain and the well when the source/drain is converted to CoSi2, a shut current experimentation has been conducted. As a result, it has been found that a sample having a large implantation energy to form concentrated p+ and n+ layers to a large depth exhibit a large amount of junction leakage. This is a result that is completely contrary to expectation. As a result of analysis, it has been found that the junction leakage is ascribed to defects due to ion implantation, and thus the sample subjected to ion implantation at a high energy and a high dose exhibits increased junction leakage.
Therefore, in the silicidation technique on the general source and drain (an Si semiconductor region), because a silicide is formed by reacting a metallic film formed on the Si semiconductor region with Si, silicide abnormally grown to be an acicular shape and a metallic atom diffused into the Si semiconductor region reach the p/n junction formed under the Si semiconductor region, or silicide is abnormally grown in the horizontal direction to reach the p/n junction at the edge part (the vicinity of the bird""s beak) of the element isolation (LOCOS) region, so as to increase the junction leakage. This problem becomes severe when CoSi2 is selected as the silicide. The abnormal growth occurs due to ion implantation damage, so-called residual defects, that occurs by ion implantation in a high concentration (about 1xc3x971020 atoms/cm2 or more) to a substrate for forming a source and drain, which is not recovered by the annealing performed later.
As one of the solutions thereof, it can be considered that the film thickness of the CoSi2 formed on the source and drain is made thin. In this case, while the junction leakage can be lowered, the object of decreasing the sheet resistance of the source and drain cannot be achieved. Furthermore, when the film thickness of the CoSi2 is decreased, the CoSi2 film is worn to the extent that it will disappear by over-etching on dry etching to form a contact hole, so as to increase the danger of increasing the contact resistance. Accordingly, the film thickness of the CoSi2 on the source and drain cannot be decreased without limitation.
Therefore, an object of the invention is to provide a method of fabricating a semiconductor device that attains a silicide contact while suppressing any increase in junction leakage electric current and deterioration in junction withstand voltage.
Another object of the invention is to provide a method of fabricating a semiconductor device having a fine wiring pattern that can be operated at a high speed.
Furthermore, a further object of the invention is to provide a method of fabricating a CMOS semiconductor device having a fine wiring pattern that can be operated at a high speed.
Still further, a more specific object of the invention is to form a CoSi2 film on a source and drain without increasing the junction leakage of a p/n junction under the source and drain. In particular, it is an object to form a CoSi2 film having a sufficient thickness to decrease the sheet residence on the source and drain without increasing the junction leakage of a p/n junction under the source and drain.
The invention comprises a first step of implanting, into a prescribed region of a semiconductor primary surface of a semiconductor main body having introduced thereto a first conductive type impurity, an ion of a second conductive type, which is the reverse of the first conductive type, to form a semiconductor region constituting a PN junction with the semiconductor; a second step of implanting, into a surface of the prescribed region, an ion of the second conductive type impurity, to form a metal-semiconductor alloy layer to a prescribed thickness; and then a step of forming, on a surface of the prescribed region having been subjected to the second step, a metal-semiconductor alloy layer formed by reacting a metal and a semiconductor.
By conducting the ion implantation by separating the ion implantation for forming the PN junction (the first step) from the ion implantation for forming the metal-semiconductor alloy layer (the second step), it becomes possible that formation of residual defects in the deep ion implantation region near the position of the PN junction will be suppressed, and in the shallow ion implantation region at the surface region, the metal-semiconductor alloy layer having a thickness sufficient to decrease the sheet resistance is formed.
The invention also comprises a first step of implanting, into a primary surface of a first semiconductor region of a first conductive type comprising silicon, an ion of a second conductive type impurity, which is the reverse of the first conductive type, to form a second semiconductor region constituting a PN junction with the first semiconductor region; a second step of implanting, into the primary surface of the first semiconductor region, an ion of the second conductive type impurity to a prescribed dose amount, to form a silicide layer to a prescribed thickness; thereafter a step of forming the second semiconductor region by a heat treatment; a step of coating a metallic layer over a surface of the second semiconductor region; and a step of reacting the metallic layer with silicon of the second semiconductor region by a heat treatment, to form a metallic silicide layer.
According to the foregoing procedures, it becomes possible that formation of residual defects in the deep ion implantation region near the position of the PN junction will be suppressed, and in the shallow ion implantation region at the surface region, the metallic silicide layer having a thickness sufficient to decrease the sheet resistance is formed. Thus, the metallic silicide layer having a low resistance that does not increase the PN junction leakage can be formed on the surface of the semiconductor region.
The invention also comprises a step of thermally oxidizing a primary surface of a first semiconductor region of a first conductive type comprising silicon, to form a gate insulating film; a step of pattern forming a gate electrode comprising polycrystalline silicon on the gate insulating film; a first step of implanting, into a part of the primary surface of the first semiconductor region not having the gate electrode formed, an ion of a second conductive type impurity; a step of forming a side wall spacer on a side wall of the gate electrode; a second step of implanting, into a part of the primary surface of the first semiconductor region not having the gate electrode and the side wall spacer formed, an ion of a second conductive type impurity, which is the reverse of the first conductive type, to form a source/drain region constituting a PN junction with the first semiconductor region; a third step of implanting, into the primary surface of the first semiconductor region, an ion of the second conductive type impurity to a prescribed dose amount, to form a silicide layer to a prescribed thickness; thereafter a step of forming a source/drain region by a heat treatment; a step of coating a metallic layer over a surface of the source/drain region and a surface of the gate electrode; and a step of reacting the metallic layer with silicon on the surface of the source/drain region and the surface of the gate electrode by a heat treatment, to form a metallic silicide layer.
According to the foregoing procedures, it becomes possible that formation of residual defects in the deep ion implantation region near the position of the PN junction will be suppressed, and in the shallow ion implantation region at the surface region, the metallic silicide layer having a thickness sufficient to decrease the sheet resistance is formed. Thus, the metallic silicide layer having a low resistance that does not increase the PN junction leakage can be formed simultaneously on the surface of the semiconductor region and the surface of the gate electrode. Therefore, a MOS semiconductor device having a fine pattern and which is suitable for high speed operation can be obtained.
The invention also relates to a method of fabricating a CMOS semiconductor device characterized by comprising a step of forming, on a primary surface of a semiconductor substrate, a first well of a first conductive type and a second well of a second conductive type; a step of forming a gate insulating film on surfaces of the first well and the second well; a step of forming, on the gate insulating film formed on the surface of the first well, a first gate electrode comprising polycrystalline silicon, and forming, on the gate insulating film formed on the surface of the second well, a second gate electrode comprising polycrystalline silicon; a first ion implantation step of implanting, into a part of a primary surface of the first well not having the first gate electrode formed, an ion of a second conductive type impurity; a second ion implantation step of implanting, into a part of a primary surface of the second well not having the second gate electrode formed, an ion of a first conductive type impurity; a step of forming, on side walls of the first and second gate electrodes, a side wall spacer; a third ion implantation step of implanting, into a part of the primary surface of the first well not having the first gate electrode and the side wall spacer formed, an ion of the second conductive type impurity, which is the reverse of the first conductive type, to form a source/drain region constituting a PN junction with the first well; a fourth ion implantation step of implanting, into the primary surface of the first well subjected to the third ion implantation step, an ion of the second conductive type impurity, to form a silicide layer to a prescribed thickness; a fifth ion implantation step of implanting, into a part of the primary surface of the second well not having the second gate electrode and the side wall spacer formed, an ion of the first conductive type impurity, to form a source/drain region constituting a PN junction with the second well; a sixth ion implantation step of implanting, into the primary surface of the second well subjected to the fifth ion implantation step, an ion of the first conductive type impurity, to form a silicide layer to a prescribed thickness; thereafter a step of forming, in the first and second wells, a source/drain region by a heat treatment; a step of coating a metallic layer over a surface of the source/drain region in the first and second well and a surface of the first and second gate electrodes; and a step of reacting the metallic layer with silicon of the surface of the source/drain region in the first and second wells and the surface of the first and second gate electrodes by a heat treatment, to form a metallic silicide layer.
According to the foregoing procedures, it becomes possible that formation of residual defects in the deep ion implantation region near the position of the PN junction in the well regions will be suppressed, and in the shallow ion implantation region at the surface region, the metallic silicide layer having a thickness sufficient to decrease the sheet resistance is formed. Thus, the metallic silicide layer having a low resistance that does not increase the PN junction leakage can be formed simultaneously on the surface of the source/drain region and the surface of the gate electrode in the well regions. Therefore, a CMOS semiconductor device having a fine pattern and which is suitable for high speed operation can be obtained.